Memory cells of a dynamic random access memory (DRAM) generally comprise a storage capacitor for storing an electrical charge that represents information to be stored, and an access transistor connected with the storage capacitor. The access transistor includes first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode controlling an electrical current flowing between the first and second source/drain regions. The gate electrode is electrically insulated from the channel by a gate dielectric. The transistor is usually partially formed in a semiconductor substrate, such as a silicon substrate. The portion in which the transistor is formed generally is denoted as the active area.
In conventional DRAM memory cell arrays, the gate electrode forms part of a word line. By addressing the access transistor via the corresponding word line, the information stored in the storage capacitor is read out.
In currently-used DRAM memory cells, the storage capacitor is implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench that extends into the substrate in a direction perpendicular to the substrate surface. According to another implementation of a DRAM memory cell, the electrical charge is stored in a stacked capacitor formed above the surface of the substrate.
The access transistor is, for example, implemented as a planar transistor, in which the channel extends horizontally along the surface of the semiconductor substrate.
A known DRAM cell has a grooved transistor, in which the gate electrode is disposed in a groove that extends in the substrate. Thereby, a current flowing from the first to the second source/drain regions and vice versa has horizontal and vertical components perpendicular to the substrate surface. This is further described in “The Breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88 nm feature size and beyond,” J. Y. Kim, et al., 2003 Symposium on VLSI Technology Dig. of Tech. Papers. A further improvement of this transistor is also known. A method of forming special contact plugs is also known.
Memory devices usually comprise a memory cell array and a peripheral portion. The peripheral portion includes support circuitry for operating the memory cell array and, for example, sense amplifiers and word line drivers.